Calculadora de Correção de Fator de Potência — Formula
## Understanding Interrupt Latency
Interrupt latency is the delay from when an interrupt occurs to when the ISR begins executing.
### Components
**Total Cycles = Sync + Pipeline Flush + Context Save + Vector Fetch**
**Latency (ns) = Total Cycles / Clock Frequency x 10^9**
### Breakdown
- **Synchronization**: Aligning the async interrupt to the clock
- **Pipeline flush**: Discarding partially executed instructions
- **Context save**: Pushing registers onto the stack
- **Vector fetch**: Reading the ISR address from the vector table
ARM Cortex-M3/M4 processors achieve 12 cycles total. Simpler 8-bit MCUs may take 4-6 cycles.
Interrupt latency is the delay from when an interrupt occurs to when the ISR begins executing.
### Components
**Total Cycles = Sync + Pipeline Flush + Context Save + Vector Fetch**
**Latency (ns) = Total Cycles / Clock Frequency x 10^9**
### Breakdown
- **Synchronization**: Aligning the async interrupt to the clock
- **Pipeline flush**: Discarding partially executed instructions
- **Context save**: Pushing registers onto the stack
- **Vector fetch**: Reading the ISR address from the vector table
ARM Cortex-M3/M4 processors achieve 12 cycles total. Simpler 8-bit MCUs may take 4-6 cycles.
Exemplo Resolvido
72 MHz ARM Cortex-M: 2 sync, 3 pipeline, 12 context save, 3 vector fetch.
- Total cycles: 2 + 3 + 12 + 3 = 20
- Latency: 20 / 72e6 x 1e9 = 277.8 ns
- Max interrupt rate: 72e6 / 20 = 3,600,000 Hz