पावर फैक्टर करेक्शन कैलकुलेटर — सूत्र

Understanding Interrupt Latency

Interrupt latency is the delay from when an interrupt occurs to when the ISR begins executing.

Components

Total Cycles = Sync + Pipeline Flush + Context Save + Vector Fetch

Latency (ns) = Total Cycles / Clock Frequency x 10^9

Breakdown

Synchronization: Aligning the async interrupt to the clock

Pipeline flush: Discarding partially executed instructions

Context save: Pushing registers onto the stack

Vector fetch: Reading the ISR address from the vector table

ARM Cortex-M3/M4 processors achieve 12 cycles total. Simpler 8-bit MCUs may take 4-6 cycles.