Calculateur de Correction du Facteur de Puissance
Calculez la correction du facteur de puissance nécessaire pour votre installation.
Cycles to synchronize the interrupt signal
Push registers to stack
Interrupt Latency
277.8 ns
Interrupt Latency vs CPU Clock
Formule
## Understanding Interrupt Latency Interrupt latency is the delay from when an interrupt occurs to when the ISR begins executing. ### Components **Total Cycles = Sync + Pipeline Flush + Context Save + Vector Fetch** **Latency (ns) = Total Cycles / Clock Frequency x 10^9** ### Breakdown - **Synchronization**: Aligning the async interrupt to the clock - **Pipeline flush**: Discarding partially executed instructions - **Context save**: Pushing registers onto the stack - **Vector fetch**: Reading the ISR address from the vector table ARM Cortex-M3/M4 processors achieve 12 cycles total. Simpler 8-bit MCUs may take 4-6 cycles.
Exemple Résolu
72 MHz ARM Cortex-M: 2 sync, 3 pipeline, 12 context save, 3 vector fetch.
- 01Total cycles: 2 + 3 + 12 + 3 = 20
- 02Latency: 20 / 72e6 x 1e9 = 277.8 ns
- 03Max interrupt rate: 72e6 / 20 = 3,600,000 Hz
Questions Fréquentes
What is worst-case interrupt latency?
Add the longest non-interruptible instruction time and any interrupt masking periods. For hard real-time systems, worst-case matters most.
Does interrupt priority affect latency?
In systems with nested interrupts, higher-priority interrupts preempt lower ones immediately. Lower-priority ones wait, increasing their worst-case latency.
How do I reduce interrupt latency?
Use a faster clock, minimize context save (use fewer registers), enable tail-chaining (ARM Cortex-M), and keep critical sections short.
Apprendre